The present invention relates, in general, to electronics and, more particularly, to structures and methods of forming semiconductor devices.
In a push to achieve smaller electronic products, manufacturers have sought ways to reduce the size of packaged electronic components. In some applications, chip level packages have been implemented where bare semiconductor die are placed directly onto a next level of assembly, such as printed circuit board. Such semiconductor die can be very small, with some being less than 1.7 millimeters (mm) by 0.8 mm.
In chip level packages, an electrical shorting problem has often occurred when the conductive material used to attach the die to the printed circuit board makes unwanted contact to side surfaces of the die being attached to the board or makes unwanted contact to adjoining devices that are placed closed by. In the past, the semiconductor industry utilized various methods to isolate edge surfaces of electronic devices to make these surfaces less susceptible to electrical shorting problems. Such methods have included deep diffusion isolations, deep trench isolations, and mesa-etched isolations as well as others. One common problem with these prior approaches is they take up significant active area on the electronic die. This adds to the overall die cost because larger die sizes are required to accommodate the isolation structures. Also, some of the prior methods require multiple photolithographic process steps and multiple thermal process steps to form the isolation structures, which adds manufacturing time and costs. Additionally, some of the prior approaches do not provide adequate isolation particularly on very small die.
Accordingly, it is desirable to have a structure and method of insulating singulated die from a semiconductor wafer that does not consume electronic die active area and that does not require expensive or additional processing steps.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.